| Server IP : 79.136.114.73 / Your IP : 3.15.147.225 Web Server : Apache/2.4.7 (Ubuntu) PHP/5.5.9-1ubuntu4.29 OpenSSL/1.0.1f System : Linux b8009 3.13.0-170-generic #220-Ubuntu SMP Thu May 9 12:40:49 UTC 2019 x86_64 User : www-data ( 33) PHP Version : 5.5.9-1ubuntu4.29 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority, MySQL : ON | cURL : ON | WGET : ON | Perl : ON | Python : ON | Sudo : ON | Pkexec : ON Directory : /usr/src/linux-headers-3.13.0-35/arch/arm/include/asm/ |
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/* * Common defines for v7m cpus */ #define V7M_SCS_ICTR IOMEM(0xe000e004) #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f #define BASEADDR_V7M_SCB IOMEM(0xe000ed00) #define V7M_SCB_CPUID 0x00 #define V7M_SCB_ICSR 0x04 #define V7M_SCB_ICSR_PENDSVSET (1 << 28) #define V7M_SCB_ICSR_PENDSVCLR (1 << 27) #define V7M_SCB_ICSR_RETTOBASE (1 << 11) #define V7M_SCB_VTOR 0x08 #define V7M_SCB_AIRCR 0x0c #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16) #define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2) #define V7M_SCB_SCR 0x10 #define V7M_SCB_SCR_SLEEPDEEP (1 << 2) #define V7M_SCB_CCR 0x14 #define V7M_SCB_CCR_STKALIGN (1 << 9) #define V7M_SCB_SHPR2 0x1c #define V7M_SCB_SHPR3 0x20 #define V7M_SCB_SHCSR 0x24 #define V7M_SCB_SHCSR_USGFAULTENA (1 << 18) #define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17) #define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16) #define V7M_xPSR_FRAMEPTRALIGN 0x00000200 #define V7M_xPSR_EXCEPTIONNO 0x000001ff /* * When branching to an address that has bits [31:28] == 0xf an exception return * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP * extension Bit [4] defines if the exception frame has space allocated for FP * state information, SBOP otherwise. Bit [3] defines the mode that is returned * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01. */ #define EXC_RET_STACK_MASK 0x00000004 #define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd #ifndef __ASSEMBLY__ enum reboot_mode; void armv7m_restart(enum reboot_mode mode, const char *cmd); #endif /* __ASSEMBLY__ */