| Server IP : 79.136.114.73 / Your IP : 18.116.26.90 Web Server : Apache/2.4.7 (Ubuntu) PHP/5.5.9-1ubuntu4.29 OpenSSL/1.0.1f System : Linux b8009 3.13.0-170-generic #220-Ubuntu SMP Thu May 9 12:40:49 UTC 2019 x86_64 User : www-data ( 33) PHP Version : 5.5.9-1ubuntu4.29 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority, MySQL : ON | cURL : ON | WGET : ON | Perl : ON | Python : ON | Sudo : ON | Pkexec : ON Directory : /lib/modules/3.13.0-49-generic/build/arch/score/include/asm/ |
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#ifndef _ASM_SCORE_SCOREREGS_H #define _ASM_SCORE_SCOREREGS_H #include <linux/linkage.h> /* TIMER register */ #define TIME0BASE 0x96080000 #define P_TIMER0_CTRL (TIME0BASE + 0x00) #define P_TIMER0_CPP_CTRL (TIME0BASE + 0x04) #define P_TIMER0_PRELOAD (TIME0BASE + 0x08) #define P_TIMER0_CPP_REG (TIME0BASE + 0x0C) #define P_TIMER0_UPCNT (TIME0BASE + 0x10) /* Timer Controller Register */ /* bit 0 Timer enable */ #define TMR_DISABLE 0x0000 #define TMR_ENABLE 0x0001 /* bit 1 Interrupt enable */ #define TMR_IE_DISABLE 0x0000 #define TMR_IE_ENABLE 0x0002 /* bit 2 Output enable */ #define TMR_OE_DISABLE 0x0004 #define TMR_OE_ENABLE 0x0000 /* bit4 Up/Down counting selection */ #define TMR_UD_DOWN 0x0000 #define TMR_UD_UP 0x0010 /* bit5 Up/Down counting control selection */ #define TMR_UDS_UD 0x0000 #define TMR_UDS_EXTUD 0x0020 /* bit6 Time output mode */ #define TMR_OM_TOGGLE 0x0000 #define TMR_OM_PILSE 0x0040 /* bit 8..9 External input active edge selection */ #define TMR_ES_PE 0x0000 #define TMR_ES_NE 0x0100 #define TMR_ES_BOTH 0x0200 /* bit 10..11 Operating mode */ #define TMR_M_FREE 0x0000 /* free running timer mode */ #define TMR_M_PERIODIC 0x0400 /* periodic timer mode */ #define TMR_M_FC 0x0800 /* free running counter mode */ #define TMR_M_PC 0x0c00 /* periodic counter mode */ #define SYSTEM_CLOCK (27*1000000/4) /* 27 MHz */ #endif /* _ASM_SCORE_SCOREREGS_H */